| Format | Description | Implementation | ECO32e |
|---|
| N | no operands | direct | - |
| R(=JR) | one register | direct | Yes |
| RH | one register and the lower 16 bits of a word | direct | - |
| RHh | one register and the upper 16 bits of a word | direct | Yes |
| RRH | two registers and a zero-extended halfword | direct | Yes |
| RRS | two registers and a sign-extended halfword | direct | Yes |
| RRR | three registers | direct | Yes |
| RRX | three registers, or two registers and a zero-extended halfword | as RRR or RRH | Yes |
| RRY | three registers, or two registers and a sign-extended halfword | as RRR or RRS | Yes |
| RRB | two registers and a sign-extended 16 bit offset | direct | Yes |
| J | no registers and a sign-extended 26 bit offset | direct | Yes |
| Mnemonic (Opcode) | Operands | Description | Format | ECO32e | Kernel only | May throw |
|---|
| add (0x00, 0x01) | dst, op1, op2 | dst := op1 + op2 | RRY | Yes | - | - |
| sub (0x02, 0x03) | dst, op1, op2 | dst := op1 - op2 | RRY | Yes | - | - |
| mul (0x04, 0x05) | dst, op1, op2 | dst := op1 * op2, signed | RRY | - | - | - |
| mulu (0x06, 0x07) | dst, op1, op2 | dst := op1 * op2, unsigned | RRX | - | - | - |
| div (0x08, 0x09) | dst, op1, op2 | dst := op1 / op2, signed | RRY | - | - | Yes |
| divu (0x0A, 0x0B) | dst, op1, op2 | dst := op1 / op2, unsigned | RRX | - | - | Yes |
| rem (0x0C, 0x0D) | dst, op1, op2 | dst := remainder of op1/op2, signed | RRY | - | - | Yes |
| remu (0x0E, 0x0F) | dst, op1, op2 | dst := remainder of op1/op2, unsigned | RRX | - | - | Yes |
| and (0x10, 0x11) | dst, op1, op2 | dst := bitwise AND of op1 and op2 | RRX | Yes | - | - |
| or (0x12, 0x13) | dst, op1, op2 | dst := bitwise OR of op1 and op2 | RRX | Yes | - | - |
| xor (0x14, 0x15) | dst, op1, op2 | dst := bitwise XOR of op1 and op2 | RRX | Yes | - | - |
| xnor (0x16, 0x17) | dst, op1, op2 | dst := bitwise XNOR of op1 and op2 | RRX | Yes | - | - |
| sll (0x18, 0x19) | dst, op1, op2 | dst := shift op1 logically left by op2 | RRX | - | - | - |
| slr (0x1A, 0x1B) | dst, op1, op2 | dst := shift op1 logically right by op2 | RRX | - | - | - |
| sar (0x1C, 0x1D) | dst, op1, op2 | dst := shift op1 arithmetically right by op2 | RRX | - | - | - |
| ldhi (0x1F) | dst, op1 | dst := op1 shifted left by 16 bits | RHh | Yes | - | - |
| beq (0x20) | op1, op2, offset | branch to PC+4+offset*4 if op1 == op2 | RRB | Yes | - | - |
| bne (0x21) | op1, op2, offset | branch to PC+4+offset*4 if op1 != op2 | RRB | Yes | - | - |
| ble (0x22) | op1, op2, offset | branch to PC+4+offset*4 if op1 <= op2 (signed) | RRB | - | - | - |
| bleu (0x23) | op1, op2, offset | branch to PC+4+offset*4 if op1 <= op2 (unsigned) | RRB | Yes | - | - |
| blt (0x24) | op1, op2, offset | branch to PC+4+offset*4 if op1 < op2 (signed) | RRB | - | - | - |
| bltu (0x25) | op1, op2, offset | branch to PC+4+offset*4 if op1 < op2 (unsigned) | RRB | Yes | - | - |
| bge (0x26) | op1, op2, offset | branch to PC+4+offset*4 if op1 >= op2 (signed) | RRB | - | - | - |
| bgeu (0x27) | op1, op2, offset | branch to PC+4+offset*4 if op1 >= op2 (unsigned) | RRB | Yes | - | - |
| bgt (0x28) | op1, op2, offset | branch to PC+4+offset*4 if op1 > op2 (signed) | RRB | - | - | - |
| bgtu (0x29) | op1, op2, offset | branch to PC+4+offset*4 if op1 > op2 (unsigned) | RRB | Yes | - | - |
| j (0x2A) | offset | jump to PC+4+offset*4 | J | Yes | - | - |
| jr (0x2B) | register | jump to register | R | Yes | - | - |
| jal (0x2C) | offset | jump to PC+4+offset*4, store PC+4 in $31 | J | Yes | - | - |
| jalr (0x2D) | register | jump to register, store PC+4 in $31 | R | - | - | - |
| trap (0x2E) | -/- | cause a trap, store PC in $30 | N | - | - | Yes |
| rfx (0x2F) | -/- | return from exception, restore PC from $30 | N | - | Yes | Yes |
| ldw (0x30) | dst, reg, offset | dst := word @ (reg+offset) | RRS | Yes | - | Yes |
| ldh (0x31) | dst, reg, offset | dst := sign-extended halfword @ (reg+offset) | RRS | Yes | - | Yes |
| ldhu (0x32) | dst, reg, offset | dst := zero-extended halfword @ (reg+offset) | RRS | Yes | - | Yes |
| ldb (0x33) | dst, reg, offset | dst := sign-extended byte @ (reg+offset) | RRS | Yes | - | Yes |
| ldbu (0x34) | dst, reg, offset | dst := zero-extended byte @ (reg+offset) | RRS | Yes | - | Yes |
| stw (0x35) | src, reg, offset | store src word @ (reg+offset) | RRS | Yes | - | Yes |
| sth (0x36) | src, reg, offset | store src halfword @ (reg+offset) | RRS | Yes | - | Yes |
| stb (0x37) | src, reg, offset | store src byte @ (reg+offset) | RRS | Yes | - | Yes |
| mvfs (0x38) | dst, special | dst := contents of special register | RH | - | - | Yes |
| mvts (0x39) | src, special | contents of special register := src | RH | - | Yes | Yes |
| tbs (0x3A) | -/- | TLB search | N | - | Yes | Yes |
| tbwr (0x3B) | -/- | TLB write random | N | - | Yes | Yes |
| tbri (0x3C) | -/- | TLB read index | N | - | Yes | Yes |
| tbwi (0x3D) | -/- | TLB write index | N | - | Yes | Yes |
| Integer Registers |
|---|
| $0 | always zero |
$8 | temporary register (caller-save) |
$16 | register variable (callee-save) |
$24 | temporary register (caller-save) |
| $1 | reserved for assembler |
$9 | temporary register (caller-save) |
$17 | register variable (callee-save) |
$25 | temporary register (caller-save) |
| $2 | func return value |
$10 | temporary register (caller-save) |
$18 | register variable (callee-save) |
$26 | reserved for OS kernel |
| $3 | func return value |
$11 | temporary register (caller-save) |
$19 | register variable (callee-save) |
$27 | reserved for OS kernel |
| $4 | proc/func argument |
$12 | temporary register (caller-save) |
$20 | register variable (callee-save) |
$28 | reserved for OS kernel |
| $5 | proc/func argument |
$13 | temporary register (caller-save) |
$21 | register variable (callee-save) |
$29 | stack pointer |
| $6 | proc/func argument |
$14 | temporary register (caller-save) |
$22 | register variable (callee-save) |
$30 | interrupt return address |
| $7 | proc/func argument |
$15 | temporary register (caller-save) |
$23 | register variable (callee-save) |
$31 | proc/func return address |